1. Field
Semiconductor integrated circuit fabrication.
2. Background
A recent development in semiconductor processing is the tri-gate transistor. A tri-gate transistor includes a thin semiconductor body (e.g., a silicon fin) formed on a substrate. A gate dielectric is formed on the top surface and the sidewalls of the fin. A gate electrode is formed on the surface of the gate dielectric on the top surface and the sidewalls of the fin. Source and drain regions are formed in the fin on opposite sides of the gate electrode. Because the gate electrode and the gate dielectric surround the semiconductor body on three sides, the transistor essentially has three separate gates. These three separate gates provide three separate channels for electrical signals to travel, thus effectively tripling the conductivity as compared to a conventional planar transistor.
Tri-gate transistors generally have superior performance to bulk gate devices. This is because of the proximity of the top and side gates to each other, which, as the fin thins, causes full depletion and results in steeper sub-threshold gradients (SG) and smaller drain induced barrier lowering (DIBL). The term “thin” hereinafter is used interchangeably with the term “narrow” to describe the dimension between the opposite sidewalls of the fin.
The SG and DIBL typically are used to determine short-channel effects (SCEs) in a transistor. In general, it is desired that SCEs are low such that the transistor off-state leakage current, Ioff (i.e., a current flowing between source and drain regions when a transistor is in an off state), remains as low as possible. A steeper SG and/or reduced DIBL indicates lower Ioff, and thus smaller and better SCEs.
Generally, the thinner the fin the smaller and better the SCEs. However, thinner fins suffer from large external resistance (Rext), which causes reduced drive current. The reduction in drive current may be measured by a change in Idsat, which is the saturated current flowing through the drain. FIG. 1A shows the DIBL of a 20 nanometer (nm)-wide fin structure (narrow fin) normalized with respect to the DIBL of a 35 nm-wide fin structure (wide fin). Both of the fins have a gate length (Lg) of 40 nm. It can be seen that the DIBL decreases substantially as the fin thins, indicating an improvement in the SCEs. However, at the same time, the thinner fin suffers greater Rext. In the example shown in FIG. 1B, the Idsat of the narrow fin is reduced by approximately 50%, which approximately matches the amount of improvement in the SCEs as seen in FIG. 1A.